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ltc6601-2 1 66012f features applications description low power, low distortion, 5mhz to 27mhz, pin con gurable filter/adc driver the ltc ? 6601-2 is a low power, low distortion, very easy-to-use fully differential 2nd order active broadband rc ? lter and driver. on-chip resistors, capacitors, and ampli? er bandwidth are trimmed to provide consistent and repeatable ? lter characteristics. the ? lter characteristics are pin-strap con? gurable. cutoff frequencies range from 5mhz to 27mhz. gain is pin-strap programmable between C17db and +17db. a three-state bias pin is provided to adjust ampli? er power consumption. select between low power (50% power reduction), high performance and standby modes with the bias pin. the ltc6601 family comes in two options which trade off distortion and noise. the ltc6601-2 offers the lowest distortion at high frequencies. the ltc6601-1 is con? g- ured for lowest noise. both are available in pin-compatible packages. the ltc6601-2 is available in a compact 4mm 4mm 20-pin leadless qfn package. 15mhz filter, single-ended input, low power mode n pin con? gurable gain and filter response up to 27mhz n low power: 16ma at 3v n low distortion (2v p-p ) 1mhz: C96dbc 2nd, C112dbc 3rd 10mhz: C65dbc 2nd, C78dbc 3rd n few external components required n resistors trimmed to 0.5% accuracy typical n capacitors trimmed to 0.5% accuracy typical n adjustable output common mode voltage n rail-to-rail output swing n power con? gurability and low power shutdown n tiny 0.75mm 20-lead (4mm 4mm) qfn package n differential a/d converter driver n antialiasing/reconstruction filter n single-ended to differential conversion/ampli? cation n low voltage, low noise, differential signal processing n common mode voltage translation n portable instrumentation 25mhz filter, single-ended input, low power mode l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6271719. typical application distortion comparison between ltc6601-1 and ltc6602-2 frequency (mhz) distortion component (dbc) 66012 ta01a C50 C80 C90 C100 C110 C70 C60 C120 1 10 100 ltc6601-1 hd2 ltc6601-2 hd2 ltc6601-1 hd3 ltc6601-2 hd3 frequency (mhz) distortion component (dbc) 66012 ta01b C40 C80 C90 C100 C110 C70 C60 C50 C120 1 10 100 ltc6601-1 hd2 ltc6601-2 hd2 ltc6601-1 hd3 ltc6601-2 hd3
ltc6601-2 2 66012f pin configuration absolute maximum ratings total supply voltage (v + to v ? ) ...............................5.5v input voltage (any pin) (note 2) ..v + + 0.3v to v ? ?0.3v input current (v ocm , bias) ..................................10ma input current (pins 1, 5) (note 2) ........................20ma input current (pins 2, 4) (note 2) ........................30ma input current (pins 6, 20) (note 2) ......................15ma input current (pins 7, 8, 9, 10, 16, 17, 18, 19) (note 2) ................................................................10ma output short-circuit duration (note 3) ............ inde? nite operating temperature range (note 4).... ?40c to 85c speci? ed temperature range (note 5) .... ?40c to 85c junction temperature ........................................... 150c storage temperature range ................... ?65c to 150c (note 1) 20 19 18 17 16 6 7 8 top view 21 uf package 20-lead (4mm s 4mm) plastic qfn 9 10 5 4 3 2 1 11 12 13 14 15 in2 + in1 + bias in1 ? in2 ? out ? v + v ? v ocm out + in4 + c5 c6 c7 c8 in4 ? c1 c2 c3 c4 t jmax = 150c, = = ( ) ( ) ( ) ( ) ( ) = = = + ( ) ( ) = ( ) = + = = = + = = = = + = = ( + ) ( + + ) ( + ) ( + ) ( )
ltc6601-2 3 66012f dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v incm = v ocm = mid-supply, bias tied to v + or ? oating, i load = 0, r bal = 100k. the ? lter is con? gured for a gain of 1 unless otherwise noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v out + + v out C )/2. v incm is de? ned as (v inp + v inm )/2. v outdiff is de? ned as (v out + C v out C ). v indiff is de? ned as (v inp C v inm ). see figure 1. symbol parameter conditions min typ max units r in (note 14) input resistance match, bias = v + single ended input resistance, pin 2 or pin 4 v s = 3v l 0.25 i b (note 7) internal ampli? er input bias v s = 2.7v to 5v bias = floating bias = v + l l C25 C50 C12.5 C25 0 0 a a i os (note 7) internal ampli? er input offset v s = 2.7v to 5v bias = floating bias = v + l l 1 1 5 10 a a v incm (note 8) input signal common mode range (v inp + v inm )/2 bias = v + , v ocm = 2.5v bias = v + , v ocm = 1.5v v s = 5v v s = 3v l l 0 0 4.7 1.7 v v bias pin floating, v ocm = 2.5v bias pin floating, v ocm = 1.5v v s = 5v v s = 3v l l 0 0 4.8 1.8 v v cmrri (notes 9, 14) input common mode rejection ratio (ampli? er input referred) v incm / v osdiff v incm = 2.5v v s = 5v 74 db cmrro (notes 9, 14) output common mode rejection ratio (ampli? er input referred) v ocm / v osdiff v ocm = 1v v s = 5v 70 db psrr (note 10) power supply rejection ratio (ampli? er input referred) v s / v osdiff bias pin floating bias = v + v s = 2.7v to 5v v s = 2.7v to 5v l l 58 58 94 81 db db psrrcm (note 10) common mode power supply rejection ratio ( v s / v oscm )v s = 2.7v to 5v l 40 51 db g cm common mode gain ( v outcm / v ocm ) v ocm = 2v v s = 5v 1 v/v common mode gain error = 100 ? (g cm C 1) v ocm = 2v v s = 5v l 0.3 1.0 % bal output balance ( v outcm / v outdiff ) single-ended input differential input v outdiff = 2v v s = 5v v s = 5v l l C58 C62 C40 C40 db db v oscm common mode offset voltage (v outcm C v ocm ) v s = 2.7v to 5v bias = floating v s = 2.7v to 5v bias = v + l l 15 15 30 30 mv mv v oscm / t common mode offset voltage drift (v outcm C v ocm ) v s = 2.7v to 5v bias = floating v s = 2.7v to 5v bias = v + l l 20 20 v/c v/c v outcmr (note 8) output signal common mode range (voltage range for the v ocm pin) v s = 3v bias pin floating v s = 5v bias pin floating v s = 3v bias = v + v s = 5v bias = v + l l l l 1.1 1.1 1.1 1.1 1.8 4 1.7 4 v v v v r invocm input resistance, v ocm pin v s = 3v l 579 k v mid voltage at the v ocm pin v s = 3v l 1.475 1.5 1.525 v
ltc6601-2 4 66012f dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v incm = v ocm = mid-supply, bias tied to v + or ? oating, i load = 0, r bal = 100k. the ? lter is con? gured for a gain of 1 unless otherwise noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v out + + v out C )/2. v incm is de? ned as (v inp + v inm )/2. v outdiff is de? ned as (v out + C v out C ). v indiff is de? ned as (v inp C v inm ). see figure 1. symbol parameter conditions min typ max units v out output voltage, high, either output pin (note 11) v s = 3v, i l = 0ma, bias pin floating v s = 3v, i l = C5ma, bias pin floating v s = 3v, i l = C20ma, bias pin floating v s = 5v, i l = 0ma, bias pin floating v s = 5v, i l = C5ma, bias pin floating v s = 5v, i l = C20ma, bias pin floating l l l l l l 240 290 470 370 430 650 450 525 850 675 775 1100 mv mv mv mv mv mv v s = 3v, i l = 0ma bias = v + v s = 3v, i l = C5ma bias = v + v s = 3v, i l = C20ma bias = v + v s = 5v, i l = 0ma bias = v + v s = 5v, i l = C5ma bias = v + v s = 5v, i l = C20ma bias = v + l l l l l l 245 285 415 350 390 550 450 525 750 625 700 1000 mv mv mv mv mv mv output voltage, low, either output pin (note 11) v s = 3v, i l = 0ma, bias pin floating v s = 3v, i l = 5ma, bias pin floating v s = 3v, i l = 20ma, bias pin floating v s = 5v, i l = 0ma, bias pin floating v s = 5v, i l = 5ma, bias pin floating v s = 5v, i l = 20ma, bias pin floating l l l l l l 110 120 170 150 170 225 200 225 300 270 300 400 mv mv mv mv mv mv v s = 3v, i l = 0ma bias = v + v s = 3v, i l = 5ma bias = v + v s = 3v, i l = 20ma bias = v + v s = 5v, i l = 0ma bias = v + v s = 5v, i l = 5ma bias = v + v s = 5v, i l = 20ma bias = v + l l l l l l 120 135 195 175 200 270 225 250 350 325 360 475 mv mv mv mv mv mv i sc output short-circuit current, either output pin (note 12) v s = 3v v s = 5v l l 45 60 65 90 ma ma v s supply voltage range l 2.7 5.25 v i s supply current, bias pin floating v s = 2.7v v s = 3v v s = 5v l l l 15.8 16 16.7 23 23.5 24.5 ma ma ma supply current, bias pin tied to v + v s = 2.7v v s = 3v v s = 5v l l l 32 32.2 33 41 41.5 43 ma ma ma i shdn supply current, bias pin tied to v C v s = 2.7v v s = 3v v s = 5v l l l 0.4 0.45 0.65 1 1.1 1.8 ma ma ma v biassd bias input pin range for shutdown v s = 2.7v to 5v l v C v C + 0.4 v v biaslp (note 13) bias input for low power operation v s = 2.7v to 5v l v C + 1.0 v C + 1.5 v v biashp bias input for high performance operation v s = 2.7v to 5v l v C + 2.3 v + v r bias bias input resistance v s = 2.7v to 5v l 100 150 200 k v bias bias float voltage v s = 2.7v to 5v l v C + 1.05 v C + 1.15 v C + 1.25 v t on turn-on time v s = 3v, v shdn = 0.25v to 3v 400 ns t off turn-off time v s = 3v, v shdn = 3v to 0.25v 400 ns
ltc6601-2 5 66012f the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v incm = v ocm = mid-supply, v bias is tied to v + or ? oating, unless otherwise noted. (see figure 2 for the ac test con? guration.) v s is de? ned as (v + C v C ). v outcm is de? ned as (v out + + v out C )/2. v icm is de? ned as (v inp + v inm )/2. v outdiff is de? ned as (v out + C v out C ). v indiff is de? ned as (v inp C v inm ). ac electrical characteristics symbol parameter conditions min typ max units gain filter gain, see figure 2, bias pin floating (remaining ac measurements relative to 1mhz) v in = 0.25v, f test = dc (note 14) v in = 600mv p-p , f test = 1mhz v in = 600mv p-p , f test = 2mhz v in = 600mv p-p , f test = 5mhz v in = 600mv p-p , f test = 10mhz v in = 600mv p-p , f test = 14.45mhz v in = 600mv p-p , f test = 20mhz v in = 600mv p-p , f test = 50mhz l l l l l l l l C0.25 C0.08 C0.01 C0.54 C3.00 C7.55 C23.55 0.05 0 0.02 0.11 C0.34 C2.50 C6.55 C21.55 0.25 0.12 0.23 C0.14 C2.00 C5.55 C19.55 db db db db db db db db phase filter phase, see figure 2, bias pin floating v in = 0.25v, f test = dc v in = 600mv p-p , f test = 1mhz v in = 600mv p-p , f test = 2mhz v in = 600mv p-p , f test = 5mhz v in = 600mv p-p , f test = 10mhz v in = 600mv p-p , f test = 14.45mhz v in = 600mv p-p , f test = 20mhz v in = 600mv p-p , f test = 50mhz l l l l l l l l C6.0 C12.5 C31.8 C70.1 C103.5 C130.7 0 C5.5 C11.3 C29.3 C65.2 C97.5 C125.1 C173.6 C4.8 C10.1 C26.8 C60.1 C91.5 C120.7 deg deg deg deg deg deg deg deg noise output noise, see figure 2, bias pin floating bw = 100mhz bw = 20mhz 154 135 v rms v rms snr bias pin floating bw = 100mhz bw = 20mhz 73 74 db db distortion v in = 2v p-p , 10mhz, bias pin floating hd2, single-ended input hd3, single-ended input hd2, differential input hd3, differential input C60 C79 C65 C77 dbc dbc dbc dbc f o tc cutoff frequency temperature coef? cient C120 ppm/c gain filter gain, see figure 2, bias pin tied to v + , ac gain measurements relative to 1mhz v in = 0.25v, f test = dc (note 14) v in = 600mv p-p , f test = 1mhz v in = 600mv p-p , f test = 2mhz v in = 600mv p-p , f test = 5mhz v in = 600mv p-p , f test = 10mhz v in = 600mv p-p , f test = 14.45mhz v in = 600mv p-p , f test = 20mhz v in = 600mv p-p , f test = 50mhz l l l l l l l l C0.25 C0.08 C0.01 C0.54 C2.75 C7.14 C23.70 0.05 0 0.02 0.11 C0.34 C2.35 C6.24 C21.70 0.25 0.12 0.23 C0.14 C1.95 C5.34 C19.70 db db db db db db db db phase filter phase, see figure 2, bias pin tied to v + v in = 0.25v, f test = dc v in = 600mv p-p , f test = 1mhz v in = 600mv p-p , f test = 2mhz v in = 600mv p-p , f test = 5mhz v in = 600mv p-p , f test = 10mhz v in = 600mv p-p , f test = 14.45mhz v in = 600mv p-p , f test = 20mhz v in = 600mv p-p , f test = 50mhz l l l l l l l l C6.0 C12.2 C31.2 C68.8 C101.5 C128.4 0 C5.4 C11 C28.7 C63.8 C95.5 C123.4 C169.3 C4.8 C9.8 C26.2 C58.8 C89.5 C118.4 deg deg deg deg deg deg deg deg noise wide band output noise, 14.45mhz cutoff, bias pin tied to v + bw = 100mhz bw = 20mhz 108 97 v rms v rms snr bias pin tied to v + bw = 100mhz bw = 20mhz 76 77 db db distortion v in = 2v p-p , 10mhz, bias pin tied to v + hd2, single-ended input hd3, single-ended input hd2, differential input hd3, differential input C67.5 C90 C70 C90 dbc dbc dbc dbc f o tc cutoff frequency temperature coef? cient C120 ppm/c
ltc6601-2 6 66012f note 1: stresses beyond those listed under the absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all pins are protected by steering diodes to either supply. if any pin is driven beyond the parts supply voltage, the excess input current (current in excess of what it takes to drive that pin to the supply rail) should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. long-term application of output currents in excess of the absolute maximum ratings may impair the life of the device. note 4: the ltc6601c/ltc6601i are guaranteed functional over the operating temperature range C40c to 85c. note 5: the ltc6601c is guaranteed to meet speci? ed performance from 0c to 70c. the ltc6601c is designed, characterized, and expected to meet speci? ed performance from C40c to 85c but is not tested or qa sampled at these temperatures. the ltc6601i is guaranteed to meet speci? ed performance from C40c to 85c. note 6: output referred voltage offset is a function of the low frequency gain of the ltc6601. to determine output referred voltage offset, or output voltage offset drift, multiply this speci? cation by the noise gain (1 + gain). see applications information for more details. note 7: input bias current is de? ned as the average of the currents ? owing into the noninverting and inverting inputs of the internal ampli? er and is calculated from measurements made at the pins of the ic. input offset current is de? ned as the difference of the currents ? owing into the noninverting and inverting inputs of the internal ampli? er and is calculated from measurements made at the pins of the ic. note 8: input common mode range is tested using the test circuit of figure 1 by measuring the differential dc gain with v icm = mid-supply, and with v icm at the input common mode range limits listed in the electrical characteristics table, verifying the differential gain has not deviated from the mid-supply common mode input case by more than 1%, and the common mode offset (v ocmos ) has not deviated from the mid-supply common mode offset by more than 20mv. the voltage range for the output common mode range is tested using the test circuit of figure 1 by measuring the differential dc gain with v ocm = mid-supply, and again with a voltage set on the v ocm pin at the electrical characteristics table limits, checking the differential gain has not deviated from the mid-supply common mode input case by more than 1%, and that the common mode offset (v ocmos ) has not deviated by more than 20mv from the mid-supply case. note 9: input cmrr is de? ned as the ratio of the change in the input common mode voltage at the ampli? er input to the change in differential input referred voltage offset. output cmrr is de? ned as the ratio of the change in the voltage at the v ocm pin to the change in differential input referred voltage offset. note 10: power supply rejection (psrr) is de? ned as the ratio of the change in supply voltage to the change in differential input referred voltage offset. common mode power supply rejection (psrrcm) is de? ned as the ratio of the change in supply voltage to the change in the common mode offset, v outcm /v ocm . note 11: output swings are measured as differences between the output and the respective power supply rail. note 12: extended operation with the output shorted may cause junction temperatures to exceed the 150c limit and is not recommended. note 13: floating the bias pin will reliably place the part into the half- power mode. the pin does not have to be driven. care should be taken, however, to prevent external leakage currents in or out of this pin from pulling the pin into an undesired state. note 14: the variable contact resistance of the high speed test equipment limits the accuracy of this test. these parameters only show a typical value, or conservative minimum and maximum value. electrical characteristics
ltc6601-2 7 66012f typical performance characteristics high performance supply current vs temperature and supply voltage shutdown supply current vs temperature and supply voltage supply current vs bias pin voltage and temperature shutdown supply current vs supply voltage and temperature low power mode supply current vs supply voltage and temperature high performance supply current vs supply voltage and temperature low power supply current vs temperature and supply voltage high performance mode differential v os vs temperature low power mode differential v os vs temperature temperature (c) C50 i cc (ma) 18.0 17.5 15.5 16.0 16.5 17.0 15.0 50 0 100 66012 g01 125 25 C25 75 v incm = v ocm = mid-supply bias pin floating 3v 5v 2.7v temperature (c) C50 i cc (ma) 35 34 31 33 32 30 50 0 100 66012 g02 125 25 C25 75 v incm = v ocm = mid-supply bias pin tied to v + 3v 2.7v 5v temperature (c) C50 i cc (ma) 0.8 0.7 0.2 0.4 0.5 0.6 0.3 0.1 0 50 0 100 66012 g03 125 25 C25 75 v incm = v ocm = mid-supply bias pin tied to v C 3v 2.7v 5v bias pin voltage with respect to v C (v) 0 i cc (ma) 50 20 30 40 10 0 1.5 0.5 2.5 66012 g04 3 12 v incm = v ocm = mid-supply v s = 3v C40c 25c 125c supply voltage (v) 0 i cc (ma) 1 0.01 0.1 0.001 3 1 66012 g05 5 24 v incm = v ocm = mid-supply bias pin tied to v C C40c 25c 125c supply voltage (v) 0 i cc (ma) 1 10 100 0.01 0.1 0.001 3 1 66012 g06 5 24 v incm = v ocm = mid-supply bias pin floating C40c 25c 125c supply voltage (v) 0 i cc (ma) 1 10 100 0.01 0.1 0.001 3 1 66012 g07 5 24 v incm = v ocm = mid-supply bias pin tied to v + C40c 25c 125c temperature (c) C50 v os input referred (mv) C0.25 1.00 0.75 0.50 0.25 0.00 C0.75 C0.50 C1.00 25 C25 66012 g08 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply bias pin tied to v + 5 representative units temperature (c) C50 v os input referred (mv) C0.25 1.00 0.75 0.50 0.25 0.00 C0.75 C0.50 C1.00 25 C25 66012 g09 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply bias pin floating 5 representative units
ltc6601-2 8 66012f typical performance characteristics low power common mode v os vs temperature internal ampli? er input bias current vs temperature bias pin input resistance vs temperature bias pin float voltage vs temperature filter input resistance vs temperature low frequency gain vs temperature high performance common mode v os vs temperature high performance mode frequency response of 12 possible filter con? gurations low power mode frequency response of 12 possible filter con? gurations temperature (c) C50 v oscm (mv) C5 10 5 0 C10 25 C25 66012 g10 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply bias pin tied to v + 5 representative units temperature (c) C50 v oscm (mv) C5 15 5 10 0 C15 C10 25 C25 66012 g11 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply bias pin floating 5 representative units temperature (c) C50 i bias (a) C20 C5 C10 C15 C30 C25 25 C25 66012 g12 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply low power mode (bias pin floating) high performance mode (bias pin tied to v + ) temperature (c) C50 resistance () 200 175 150 100 125 25 C25 66012 g13 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply temperature (c) C50 float voltage (v) 1.20 1.15 1.10 1.00 1.05 25 C25 66012 g14 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply temperature (c) C50 resistance/r nominal (/) 1.0050 1.0025 1.0000 0.9950 0.9975 25 C25 66012 g15 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply r nominal = 200 differential r nominal = 133.3 single-ended see figure 1 for configuration single-ended differential temperature (c) C50 gain (v/v) 1.010 1.005 1.000 0.990 0.995 25 C25 66012 g16 125 0 50 75 100 v s = 3v v incm = v ocm = mid-supply 5 representative units frequency (mhz) gain (db) 66012 g17 10 0 C10 C20 C30 0.1 10 100 1 v s = 3v v incm = v ocm = mid-supply bias pin tied to v + frequency (mhz) gain (db) 66012 g18 10 0 C10 C20 C30 0.1 10 100 1 v s = 3v v incm = v ocm = mid-supply bias pin floating
ltc6601-2 9 66012f typical performance characteristics low power mode gain and phase repeatability of 10 random units high performance mode gain error of 10 random units normalized to 1mhz low power mode gain error of 10 random units normalized to 1mhz high performance mode phase error of 10 random units low power mode phase error of 10 random units turn on and turn off transient response high performance mode gain and phase repeatability of 10 random units pulse response frequency (mhz) gain deviation (db) phase deviation (deg) 66012 g19 0.20 00 0.05 0.10 0.15 C0.10 C0.05 C0.15 C0.20 4 1 2 3 C2 C1 C3 C4 0.1 10 100 1 v s = 3v v incm = v ocm = mid-supply bias pin tied to v + see figure 1 max C average min C average j max C j average j min C j average frequency (mhz) gain deviation (db) phase deviation (deg) 66012 g20 0.20 00 0.05 0.10 0.15 C0.10 C0.05 C0.15 C0.20 4 1 2 3 C2 C1 C3 C4 0.1 10 100 1 v s = 3v v incm = v ocm = mid-supply bias pin floating see figure 1 max C average min C average j max C j average j min C j average frequency (mhz) gain error (db) 66012 g21 3 2 1 0 C3 C2 C1 1 10 100 v s = 3v v icm = v ocm = mid-supply bias pin tied to v+ 10 random units plotted t a = 25c +specification Cspecification frequency (mhz) gain error (db) 66012 g22 3 2 1 0 C3 C2 C1 1 10 100 v s = 3v v icm = v ocm = mid-supply bias pin floating 10 random units plotted t a = 25c +specification Cspecification frequency (mhz) phase error (deg) 66012 g23 8 6 4 2 0 C8 C6 C4 C2 1 10 100 v icm = v ocm = mid-supply v s = 3v t a = 25c +specification Cspecification bias pin tied to v+ 10 random units plotted frequency (mhz) phase error (deg) 66012 g24 8 6 4 2 0 C8 C6 C4 C2 1 10 100 v icm = v ocm = mid-supply v s = 3v t a = 25c +specification Cspecification bias pin floating 10 random units plotted time (s) 0 v outdiff (v) v bias pin (v) 5 4 3 2 1 0 C3 C2 C1 C5 C4 1.6 1.4 1.2 1.0 0.8 0.2 0.4 0.6 0 2 66012 g25 6 1345 v s = 5v bias pin v outdiff time (s) 0 v outdiff (v) 2 1 0 C1 C2 2 66012 g26 8 1 34567 v s = 3v
ltc6601-2 10 66012f typical performance characteristics normalized 100 resistor trim normalized 125 resistor trim differential output noise distortion vs frequency % change of f o vs temperature passband gain and phase vs temperature gain error relative to 1mhz vs temperature phase error vs temperature distortion vs frequency frequency (mhz) noise spectral density (nv/ hz ) integrated noise (v rms ) 66012 g27 100 1 10 0.1 1000 10 100 1 0.001 0.01 10 100 1 0.1 v s = 3v integrated noise, bias tied to v + spectral density, bias tied to v + spectral density, bias pin floating integrated noise, bias pin floating frequency (mhz) harmonic (dbc) 66012 g28 C60 C70 C120 C110 C100 C90 C80 C130 0.1 10 100 1 v s = 5v v in = 2v p-p input v icm = v ocm = mid-supply bias pin tied to v+ single ended input differential input hd2 hd3 frequency (mhz) harmonic (dbc) 66012 g29 C50 C60 C110 C100 C90 C80 C70 C120 0.1 10 100 1 v s = 5v v in = 2v p-p input v icm = v ocm = mid-supply bias pin floating single ended input differential input hd2 hd3 temperature (c) C50 change of f o (%) 0.5 0 C0.5 C2.0 C1.0 C1.5 25 C25 66012 g30 125 0 50 75 100 frequency (mhz) gain (db) phase (deg) 66012 g31 0.5 C3.0 v s = 3v v icm = v ocm = mid-supply bias pin tied to v+ temperatures plotted: C45c, C10c, 25c, 70c, 95c, 125c 110 C2.5 C2.0 C1.5 C1.0 C0.5 0 0 C105 C90 C75 C60 C45 C30 C15 gain phase frequency (mhz) gain error (db) 66012 g32 3 2 1 0 C3 C2 C1 1 10 100 v s = 3v v icm = v ocm = mid-supply bias pin tied to v+ temperatures plotted: C45c, C10c, 25c, 70c, 95c, 125c +specification Cspecification frequency (mhz) phase error (db) 66012 g33 15 10 5 0 C15 C10 C5 1 10 100 v s = 3v v icm = v ocm = mid-supply bias pin tied to v+ temperatures plotted: C45c, C10c, 25c, 70c, 95c, 125c +specification Cspecification normalized resistance 0.993 frequency 900 100 700 500 300 800 600 400 200 0 1.005 66012 g34 1.009 1.001 0.997 average = 100 std. dev = 0.19 normalized resistance 0.99 frequency 1000 100 700 500 300 800 900 600 400 200 0 1.006 1.002 66012 g35 1.01 0.998 0.994 average = 125 std. dev = 0.22
ltc6601-2 11 66012f typical performance characteristics normalized input 400 resistor trim normalized feedback 400 resistor trim normalized 21.1pf capacitor trim normalized 33.3pf capacitor trim normalized 48.2pf capacitor trim normalized 81.5pf capacitor trim normalized 10.55pf capacitor trim normalized 16.1pf capacitor trim normalized 200 resistor trim normalized resistance 0.99 frequency 1000 100 700 500 300 800 900 600 400 200 0 1.006 1.002 66012 g36 1.01 0.998 0.994 average = 200 std. dev = 0.37 normalized resistance 0.99 frequency 900 100 700 500 300 800 600 400 200 0 1.006 1.002 66012 g37 1.01 0.998 0.994 average = 400.01 std. dev = 1.0 normalized resistance 0.99 frequency 1000 100 700 500 300 800 900 600 400 200 0 1.006 1.002 66012 g38 1.01 0.998 0.994 average = 400.01 std. dev = 0.87 normalized capacitance 0.984 frequency 1200 800 1000 600 400 200 0 1.009 1.003 66012 g39 1.015 0.997 0.990 average = 21.1pf std. dev = 0.07pf normalized capacitance 0.988 frequency 1000 800 700 900 600 500 400 300 200 100 0 1.010 1.005 66012 g40 1.016 0.999 0.993 average = 33.3pf std. dev = 0.09pf normalized capacitance 0.995 0.992 frequency 1200 800 1000 600 400 200 0 1.007 1.004 66012 g41 1.010 1.001 0.998 average = 48.2pf std. dev = 0.08pf normalized capacitance 0.996 0.993 frequency 1000 800 700 500 300 100 900 600 400 200 0 1.007 1.004 66012 g42 1.010 1.002 0.999 average = 81.5pf std. dev = 0.1pf normalized capacitance 0.991 0.987 frequency 400 300 250 150 50 350 200 100 0 1.009 1.005 66012 g43 1.014 1.000 0.996 average = 10.55pf std. dev = 0.03pf normalized capacitance 0.995 0.992 0.988 frequency 350 300 250 150 50 200 100 0 1.010 1.006 66012 g44 1.014 1.003 0.999 average = 16.1pf std. dev = 0.05pf
ltc6601-2 12 66012f pin functions in1 + , in2 + , in4 + (pins 2, 1, 20): input to a trimmed 100, 200, 400 resistor which feeds a noninverting summing node. can accept an input signal, be ? oated or tied to out C . for best performance, stray capacitance should be kept as low as possible by keeping printed circuit connections as short and direct as possible. if necessary, strip back the surrounding ground plane away from these pins. bias (pin 3): input to a three-state comparator whose three states allow the user to tailor ampli? er power. the pin impedance appears as a 150k resistor whose default open-circuit potential is 1.15v with respect to the v C power supply. if bias is driven to within 0.4v of the v C supply, the ampli? er is placed into a low power shutdown, consum- ing typically 450a. when bias is ? oated, the ampli? er operates in its low power active state. forcing the pin 2.3v above v C places the part into the high performance active state. see applications information for more detail. in1 C , in2 C , in4 C (pins 4, 5, 6): input to a trimmed 100, 200, 400 resistor which feeds an inverting summing node. can accept an input signal, be ? oated or tied to out + . for best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby sur- rounding ground plane away from these pins. c1, c2 (pins 7, 8): input to a trimmed 16.1pf, 33.3pf capacitor which feeds a noninverting summing node. typically, either ? oat or tie to out C . if either of these pins is tied to a low impedance source other than out C , a resistance of at least 25 should be placed in series. for best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. c3, c4 (pins 9, 10): input to a trimmed 10.55pf, 21.1pf capacitor which feeds the ampli? er inverting summing node. typically, either ? oat or tie to out + . for best per- formance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if nec- essary, stripping back nearby surrounding ground plane away from these pins. out + , out C (pins 11, 15): output pins. besides driving the internal feedback network, each pin can drive an ad- ditional 50 to ground with typical short-circuit current limiting of 65ma. capacitive loading of these pins should be minimized by resistively decoupling the outputs from the load with at least 25. v ocm (pin 12): output common mode reference voltage. the voltage on v ocm sets the output common mode voltage level (which is de? ned as the average of the voltages on the out + and out C pins). the v ocm pin is the midpoint of an internal resistive voltage divider between the sup- plies, developing a (default) mid-supply voltage potential to maximize output signal swing. the v ocm pin can be overdriven by an external voltage reference capable of driving the input impedance presented by the v ocm pin. the v ocm pin has an input resistance of approximately 7k to a mid-supply potential. it should be bypassed with a high quality ceramic bypass capacitor (for instance of x7r dielectric) of at least 0.01f, (unless using symmetrical split supplies, then connect directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the ic. (refer to the block diagram)
ltc6601-2 13 66012f v + , v C (pins 14, 13): power supply pins. it is critical that close attention be paid to supply bypassing. for single supply applications (pin 13 grounded), it is recommended that a high quality 0.1f surface mount ceramic bypass capacitor (x7r dielectric for instance) be placed between pins 14 and 13, with direct short connections. pin 13 should be tied directly to a low impedance ground plane with minimal routing. for dual (split) power supplies, it is recommended that at least two additional high quality 0.1f ceramic capacitors are used to bypass v + to ground and v C to ground, again with minimal routing. for driving large loads (< 200), additional bypass capacitance may be added for optimal performance. keep in mind that small geometry (e.g., 0603) surface mount ceramic capacitors have a much lower esl than do leaded capacitors, and perform best in high speed applications. c7, c8 (pins 17, 16): input to a trimmed 10.55pf, 21.1pf capacitor which feeds the ampli? er noninverting sum- ming node. typically, either ? oat or tie to out C . for best performance, stray capacitance should be kept as low as possible by keeping printed circuit connections as short and direct as possible.if necessary, strip back the sur- rounding ground plane away from these pins. c5, c6 (pins 19, 18): input to a trimmed 16.1pf, 33.3pf capacitor which feeds an inverting summing node. typi- cally, either ? oat or tie to out + . if either of these pins are tied to a low impedance source other than out + , a re- sistance of at least 25 should be placed in series. for best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding reference plane away from these pins. exposed pad (pin 21): always tie the underlying exposed pad to v C (pin 13). if split supplies are used, do not tie the pad to ground. tie it to v C . pin functions (refer to the block diagram)
ltc6601-2 14 66012f block diagram 860 400 400 48.2pf 125 bias 125 200 in2 + in1 + 100 21.1pf 10.55pf 21.1pf 48.2pf 10.55pf 81.5pf 81.5pf 33.3pf c2 c1 v ocm 860 14k 14k 12 out + 11 out C 15 v + v C 14 13 33.3pf c6 8 16.1pf 18 16.1pf 400 c5 19 in4 + c7 17 c8 16 c3 9 c4 66012 bd 10 7 in4 C 400 1 2 bias 100 in1 C in2 C 200 4 5 3 6 20 + C 60k 180k 180k v C + 2.3v
ltc6601-2 15 66012f test circuits + C 0.1f v out C 0.01f bias v inp v inm 0.1f 0.1f v + 25 v C v ocm v out(cm) r bal i l r bal 66012 f01 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 + C + C v out + 25 i l ltc6601-2 figure 1. dc test circuit + C 0.1f v out C 0.01f bias 1f 1f 1f 1f coilcraft ttwb-4-b 0.1f 0.1f v + 100 50 v C v ocm 66012 f02 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v out + 100 v in ltc6601-2 lt6411 13 14 15 16 8 5 69 5v C5v 10 11 12 123717 v inp v inm figure 2. ac test circuit (frequency response testing)
ltc6601-2 16 66012f applications information functional description the ltc6601 is designed to make the implementation of high frequency fully-differential ? ltering functions very easy. a very low noise ampli? er is surrounded by 8 precision matched resistors and 12 precision matched capacitors so that a myriad of ? lter transfer functions limited only by possible combinations and imagination can be con? gured by hard wiring pins. the ampli? er itself is a wide band, low noise and low distortion fully-differential ampli? er with ac- curate output phase balancing. it is optimized for driving low voltage, single-supply, differential input, analog-to-digital converters (adcs). the ltc6601s outputs are capable of swinging rail-to-rail on supplies as low as 2.7v, which makes the ampli? er ideal for converting ground referenced, single-ended signals into v ocm referenced differential signals. unlike traditional op amps which have a single output, the ltc6601 has two outputs to process signals differentially. this allows for two times the signal swing in low voltage systems when compared to single-ended output ampli? ers. the balanced differential nature of the ampli? er and matched surrounding components provide even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). the ltc6601 can be used as a single-ended input to differential output ampli? er, or as a differential input to differential output ampli? er. figure 3 shows the basic ? lter architecture. the laplace transfer function from v indiff to v outdiff is given by the following generalized equation for a 2nd order lowpass ? lter: v outdiff v indiff = gain 1 + s 2 f o ?q + s 2 2 f o () 2 both gain and q of the ? lter are based on component ratios, which match and track extremely well over temperature. the corner frequency of the ? lter is a function of an rc product. this rc product is trimmed to 1% (typical) and is not expected to drift by more than 1% from nominal over the entire temperature range C40c to 85c. as a result, fully differential ? lters with tight magnitude, phase tolerance and repeatability are achieved. although figure 3 implies a differential input, the ltc6601 easily accepts single-ended inputs to either input, and will faithfully replicate the signal at the output in differential form. the ltc6601s output common mode voltage, de? ned as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by apply- ing a voltage on the v ocm pin. if the pin is left open, there is an internal resistive voltage divider, which develops a figure 3. basic filter topology and equations C C + + c1 r3 r2 r2 r3 r1 r1 c2 c1 v out(diff) 66012 f03 v in(diff) c2 f o = 1 2 r2 ? r3 ? c1 ? c2 q= c2 c1 r3 r2 ? 1 1+ 1+ gain ? r3 r2 C c2 c1 gain = r2 r1 f 3db = f o ? 6089 ? 3568 ? q 4 1788 ? q 2 + 447 () + 1.287 ? 10 5 ?2?q 2 1 () 507.6 ? q q = 0.2236 ? f o ? 2.109 ? 10 5 ? 9.891? 10 12 ?f 3db 4 5.486 ? 10 9 ?f o 4 () + 120 ? 5.526 ? 10 9 ?f 3db 2 + 3.082 ? 10 6 ?f o 2 () 16 ? f o 2 ? 8.29 ? 10 9 ?f 3db 2 + 4.127 ? 10 9 ?f o 2 () 6.638 ? 10 10 ?f 3db 4 ()
ltc6601-2 17 66012f applications information potential halfway between the v + and v C pins. whenever this pin is not hard tied to a low impedance ground plane, a high quality ceramic capacitor should be used to bypass the v ocm pin to a low impedance ground plane (see layout considerations). the ltc6601s internal common mode feedback path forces accurate output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the v ocm pin. v outcm = v ocm = v out + + v out ? 2 the outputs (out + and out C ) of the ltc6601 are capable of swinging rail-to-rail. they can source or sink up to ap- proximately 75ma of current. load capacitances should be decoupled with at least 25 of series resistance from each output. the ltc6601 electrical characteristics table speci? es an input referred offset. this speci? cation actually lumps volt- age offsets due to offset bias currents (i os ), and ampli? er voltage offset into one speci? cation. to refer this speci? ca- tion to the output, you simply multiply the speci? cation by the noise gain the ltc6601 is con? gured in: v osodiff = 1 + gain where gain is the closed loop gain in the particular ? lter application: gain = r2 r1 component input pin protection all of the ltc6601 pins with the exception of v + and v C are protected with steering diodes to either power supply. in the event that a pin is driven beyond the supply rails, the excess current should be limited to under 10ma to prevent damage to the ic. bias pin the ltc6601 has a bias pin (pin 3) whose function is to tailor both performance and power of the ltc6601. the pin has a thevenin equivalent impedance of approximately 150k to a voltage source whose potential is 1.15v above the v C supply. this pin has ? xed logic levels relative to v C (see the electrical characteristics table), and can be driven by an external source keeping in mind its equivalent input impedance and equivalent input voltage. if the bias pin is ? oated, care should be taken to control external leakage currents to this pin to under 1a to prevent putting the ltc6601 an undesired state. if bias is tied to the positive supply, the ltc6601 dif- ferential ? lter will be in a fully active state con? gured for highest performance (lowest noise and lowest distortion). if the bias pin is ? oated or left unconnected, the ltc6601 ? lter will be in a fully active state, with ampli? er currents reduced and performance scaled back to preserve power consumption. if the bias pin is tied to the most negative supply (v C ), the ltc6601 will be placed into a low power shutdown mode with ampli? er outputs disabled. in this state, the ltc6601 draws approximately 450a. in low power shutdown, all internal biasing current sources are shut off, and the output pins, out + and out C , will each appear as open collectors with a non-linear capacitor in parallel and steering diodes to either supply. the turn-on and turn-off time constant between states are on the order of 0.4s. using this function to wire-or outputs together is not recommended. general design and usage as levels of integration have increased and correspond- ingly, system supply voltages decreased, there has been a need for adcs to process signals differentially in order to maintain good signal-to-noise ratios. these adcs are typically supplied from a single supply voltage which can be as low as 3v (2.7v min), and will have an optimal common mode input range near mid-supply. the ltc6601 makes interfacing to these adcs easy, by providing anti- alias ? ltering, single-ended to differential conversion and common mode level shifting (translation). figure 3 shows a general application of this. the low frequency gain to v outdiff from v in is simply: v outdiff = v out + ?v out ? r2 r1 ?v indiff the differential output voltage (v out + C v out C ) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. this makes the
ltc6601-2 18 66012f ltc6601 ideally suited for pre-ampli? cation, level shift- ing and conversion of single-ended signals to differential output signals for driving differential input adcs. input impedance calculating the low frequency input impedance of the ltc6601 depends on how the inputs are driven (whether they are driven from a single-ended or a differential source). figure 4 shows a simpli? ed low frequency equivalent circuit of the ltc6601. for balanced input sources (v inp = Cv inm ), the low frequency input impedance is given by the equation: r inp = r inm = r1 the differential input impedance is simply: r indiff = 2 ? r1 for single-ended inputs (v inm = 0), the input impedance actually increases over the balanced differential case due to the fact the summing node (at the junction of r1, r2 and r3) moves in phase with v inp to bootstrap the input impedance. referring to figure 4 with v inm = 0, the input impedance looking into either input is: r inp = r inm r1 1? 1 2 ? r2 r1 + r2

input and output common mode voltage range the input common mode voltage is de? ned as the average of the two inputs: v incm = v inp + v inm 2 the lower limit of the input common mode range is dic- tated by the esd protection diodes at the input. while it is possible for the inputs to swing below v C , the diodes will conduct if the inputs are taken a diode drop below v C . the upper limit of the input common mode range varies as a function of the ? lter con? guration (gain), v ocm po- tential, and whether or not the inputs are single-ended or differential. while it is possible to exceed the upper limit of the common mode range, doing so will degrade ? lter linearity. referring to figure 4, for linear operation, the summing junction where r1, r2 and r3 merge together should be prevented from swinging to within 1.4v of the v + power supply. for the general case, the upper input common mode volt- age limit should be constrained to: v ocm ? r1 r1 + r2 + v incm ? r2 r1 + r2 v + ? 1.4v or equivalently: v incm 1 + r1 r2
v + ? 1.4v () ? r1 r2 ?v ocm the speci? cations for input common mode range (v incmr ) are based on these constraints with r1 = r2 = 100, and v ocm = mid-supply. substituting the numbers for a single 3v power supply, (v + = 3v, v C = 0v) with v ocm =1.5v, and r1 = r2 = 100, into the above equation, the input com- mon mode range (v incmr ) is between the two limits: 0v v incm 1.7v which is as is speci? ed for a 3v supply. applications information C + r2 v out C v out + v ocm v outdiff 0.1f 66012 f04 r1 r inp v inp v inm r1 r2 r3 r3 + + C C + C r inm figure 4. input impedance
ltc6601-2 19 66012f likewise, substituting the numbers for a single 5v power supply, (v + = 5v, v C = 0v) with v ocm = 2.5v, and r1 = r2 = 100, into the above equation, the input common mode range (v incmr ) is between the two limits: 0v v incm 4.7v the output common mode voltage is de? ned as the aver- age of the two outputs: v outcm = v ocm = v out + + v out ? 2 the v ocm pin sets this average by an internal common mode feedback loop which internally forces v out + = Cv out C. the output common mode range extends from 1.1 v above v C to 1v below v + . the v ocm pin sits in the middle of a voltage divider which sets the default mid- supply open circuit potential. in single supply applications, where the ltc6601 is used to interface to an adc, the optimal common mode input to the adc is often determined by the adcs reference. if the adc makes a reference available for setting the input common mode voltage, it can be directly tied to the v ocm pin, but must be capable of driving the input impedance of the v ocm pin (r vocm ). this impedance can be assumed to be connected to a mid-supply potential. if an external reference drives the v ocm pin, it should still be bypassed with a high quality 0.01f or higher capacitor to a low impedance ground plane to ? lter any thermal noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals. noise considerations when comparing the ltc6601 noise to other ampli? ers, be sure to compare similar speci? cations. competing devices often specify noise referred to the inputs of the ampli? er. the input referred voltage noise of the ltc6601-2 is 4.7nv/ hz . in addition to the noise generated by the ampli? er, the surrounding feedback resistors also contribute noise. a noise model is shown in figure 5. the output spot noise generated by both the ampli? er and the feedback compo- nents is governed by the equation: applications information e no = e ni ?1 + r2 r1

2 + 2? i n 2 ?r2 2 + r3 2 ?1 + r2 r1
2

+ 2? e nr1 ? r2 r1

2 + 2e nr3 ?1 + r2 r1

2 + 2?e nr2 2 substituting the equation for johnson noise of a resistor (e nr = 4ktr), and simplifying: e no = e ni ?1 + r2 r1

2 + 2? i n 2 ?r2 2 + r3 2 ?1 + r2 r1
2

+ 8?k?t r2 1 + r2 r1
+ r3 1 + r2 r1
2

ltc6601-2 20 66012f applications information table 1 lists the ampli? er input referred noise for the ltc6601-2. tables 2 to10 list the noise referred to the input pins of the ic for common con? gurations of the ltc6601-2. to determine the spot noise at the output, simply multiply the noise by the gain = r2/r1. to estimate the integrated noise at the output, multiply the noise by the gain, and the square root of the noise bandwidth. the noise bandwidth depends on the ? lter con? guration. for figure 2, the noise bandwidth is 100mhz, or approximately 7 times the ? lter bandwidth. improvements in snr can be made by adding an additional rc ? lter at the output to band limit wide band noise before feeding adcs. see the section interfacing the ltc6601 to adc converters for more detail. table 1. ampli? er (input referred) noise characteristics for the ltc6601-2 bias pin pulled to v + bias pin floating e ni nv/ hz i n pa/ hz e ni nv/ hz i n pa/ hz 4.7 3 5.2 2.1 layout considerations because the ltc6601 is a very high speed ampli? er, it is sensitive to both stray capacitance and stray inductance. it is critical that close attention be paid to supply bypass- ing. for single supply applications, it is recommended that a high quality 0.1f surface mount ceramic bypass capacitor be placed between pins 14 and 13 with direct short connections. pin 13 and the exposed pad, pin 21, should be tied directly to a low impedance ground plane with minimal routing. for dual (split) power supplies, it is recommended that an additional high quality, 0.1f ceramic capacitor be used to bypass pin v + to ground and v C to ground, again with minimal routing. for driv- ing large differential loads (<200), additional bypass capacitance may be needed between v + and v C for opti- mal performance. note that small geometry (e.g., 0603) surface mount ceramic capacitors have a much higher self resonant frequency than capacitors with leads, and perform best in high speed applications. the v ocm pin should be bypassed to ground with a high quality ceramic capacitor whose value exceeds 0.01f, with direct, short connections. in split supply applications, the v ocm pin can be either bypassed to ground or directly hardwired to ground. be careful not to violate the output common mode range speci? cations for the v ocm pin. stray parasitic capacitances to unused component pins that set up the ? lters characteristics, should be kept to an absolute minimum. this prevents deviations from the ideal frequency response. an ideal layout technique would be to remove the solder pads for the unused component pins, and strip away the ground plane underneath these pins to lower capacitance to an absolute minimum. floating unused component pins which set up the ? lter characteristics will not reduce the reliability of the ltc6601. at the output, always keep in mind the differential nature of the ltc6601, and that it is critical that the load impedances seen by both outputs (stray or intended), should be as bal- anced and symmetric as possible. this will help preserve the natural balance of the ltc6601, which minimizes the generation of even order harmonics and preserves the rejection of common mode signals and noise. C + 66012 f05 r1 r1 r3 * * e ni 2 e no 2 e nr3 2 r3 * e nr3 2 r2 * e nr2 2 r2 * e nr2 2 * e nr1 2 * e nr1 2 i n + 2 i n C 2 figure 5. differential noise model of the ltc6601
ltc6601-2 21 66012f applications information interfacing the ltc6601 to adc converters the ltc6601s rail-to-rail differential output and adjustable output common mode voltage make the ltc6601 ideal for interfacing to low voltage, single supply, differential input adcs. the sampling process of adcs creates a sampling transient that is caused by the switching-in of the adc sampling capacitor. the switching-in of this sampling capacitor momentarily shorts the output of the ampli? er as charge is transferred between ampli? er and sampling capacitor. the ampli? er must recover and settle from this load transient before this acquisition period has ended, for a valid representation of the input signal. the ltc6601 will settle much more quickly from these peri- odic load impulses than it does from a 2v input step, but it is a good idea to add an rc network after the outputs of the ltc6601 to decouple the sampling transient of the adc (see figure 6). the capacitance of the decoupling network serves to provide the bulk of the charge during the sampling process, while the two resistors of the ? lter network are used to dampen and attenuate any transient induced by the adc. the adcs sampling bandwidth will often be much greater than that of the ltc6601, so hav- ing this discrete rc ? lter will give the additional bene? t of band limiting broadband output noise. the selection of the rc time constant is trial and error for a given adc, but the following guidelines are recom- mended. choose an rc pole frequency greater than the cutoff frequency of the ltc6601. 80mhz rc ? lters are good for ? ltering broadband noise. lower frequency rc ? lters improve snr at the expense of settling time. the resistors in the decoupling network should be at least 25. too much resistance in the decoupling network leaves insuf? cient settling time and will create a voltage divider between the dynamic input impedance of the adc and the decoupling resistors. using insuf? cient resistance might prevent proper dampening of the load transient caused by the sampling process, and prolong the time required for settling. in 16-bit applications, this will typically require a minimum of 11 rc time constants. it is recommended that the capacitor is chosen with low dielectric absorption (such as a c0g multilayer ceramic capacitor). + C 0.1f v out C v out + 10nf bias 1f c1 c2 3v r r v ocm 66012 f06 c1 t = r ? (c1 + 2 ? c2) 2.2f 1f 1f 3.3v d15 ? ? d0 v in + C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a in + a in C v cm gnd control ltc6601-2 1f figure 6. interfacing the ltc6601 to a/d converters
ltc6601-2 22 66012f applications information a gallery of basic filter topologies tables 2 through 10 list (sorted by gain) a hundred possible ? lter topologies that can be easily implemented with the ltc6601. the tables also list the ltc6601-2 approximate midband (1mhz) spot noise e in referred to the input re- sistor, r1 (with the bias pin pulled to v + ). the gains for these topologies range from 1v/v to 7v/v. the qs listed are within the range of 0.54 and 1.72. the f o s listed are in the range of 6.96mhz and 22.71mhz, and the C3db frequencies listed range from 5.5mhz to 27.5mhz. for all ? lters listed, r3 = 125. figures 7 to 10 show how to pin-strap each ? lter con? guration. table 2. gain of 7 filter con? gurations gain f o (mhz) f C3db (mhz) q r1 ( ) r2 ( ) c1 (pf) c2 (pf) e in (nv/ hz ) v/v db 7.0 16.902 10.38 7.43 0.539 57.14 400.00 48.2 97.6 6.1 7.0 16.902 9.57 10.36 0.771 57.14 400.00 48.2 114.8 6.1 7.0 16.902 8.96 12.10 1.175 57.14 400.00 48.2 130.9 6.1 7.0 16.902 8.12 7.49 0.656 57.14 400.00 58.75 130.9 6.1 table 3. gain of 6 filter con? gurations gain f o (mhz) f C3db (mhz) q r1 ( )r2 ( )c1 (pf) c 2 (pf) e in (nv/ hz ) v/v db 6.0 15.563 10.38 10.03 0.684 66.67 400.00 48.2 97.6 6.2 6.0 15.563 9.57 12.52 1.071 66.67 400.00 48.2 114.8 6.2 6.0 15.563 8.67 7.67 0.634 66.67 400.00 58.75 114.8 6.2 6.0 15.563 8.12 9.59 0.870 66.67 400.00 58.75 130.9 6.2 6.0 15.563 7.47 6.07 0.592 66.67 400.00 69.3 130.9 6.2 table 4. gain of 5 filter con? gurations gain f o (mhz) f C3db (mhz) q r1 ( )r2 ( ) c1 (pf) c2 (pf) e in nv/ hz v/v db 5.0 13.979 11.36 9.67 0.614 80.00 400.00 48.2 81.5 6.5 5.0 13.979 10.38 12.78 0.936 80.00 400.00 48.2 97.6 6.5 5.0 13.979 9.40 7.67 0.594 80.00 400.00 58.75 97.6 6.5 5.0 13.979 8.67 10.07 0.849 80.00 400.00 58.75 114.8 6.5 5.0 13.979 8.12 11.25 1.290 80.00 400.00 58.75 130.9 6.5 5.0 13.979 7.98 6.46 0.591 80.00 400.00 69.3 114.8 6.5 5.0 13.979 7.47 8.16 0.779 80.00 400.00 69.3 130.9 6.5 5.0 13.979 6.96 5.50 0.579 80.00 400.00 79.85 130.9 6.5
ltc6601-2 23 66012f table 5. gain of 4 filter con? gurations gain f o (mhz) f C3db mhz q r1 ( )r2 ( ) c1 (pf) c2 (pf) e in nv/ hz v/v db 4.0 12.041 11.36 13.05 0.834 100.00 400.00 48.2 81.5 6.8 4.0 12.041 10.38 14.80 1.480 100.00 400.00 48.2 97.6 6.8 4.0 12.041 9.40 10.47 0.799 100.00 400.00 58.75 97.6 6.8 4.0 12.041 8.67 12.00 1.284 100.00 400.00 58.75 114.8 6.8 4.0 12.041 8.65 6.76 0.575 100.00 400.00 69.3 97.6 6.8 4.0 12.041 7.98 8.84 0.794 100.00 400.00 69.3 114.8 6.8 4.0 12.041 7.43 6.09 0.596 100.00 400.00 79.85 114.8 6.8 4.0 12.041 7.47 10.00 1.141 100.00 400.00 69.3 130.9 6.8 4.0 12.041 6.96 7.57 0.775 100.00 400.00 79.85 130.9 6.8 table 6. gain of 3 filter con? gurations gain f o (mhz) f C3db (mhz) q r1 ( ) r2 ( ) c1 (pf) c2 (pf) e in (nv/ hz ) v/v db 3.0 9.542 16.06 12.36 0.568 66.67 200.00 48.2 81.5 7.1 3.0 9.542 14.68 15.74 0.763 66.67 200.00 48.2 97.6 7.1 3.0 9.542 13.53 17.83 1.091 66.67 200.00 48.2 114.8 7.1 3.0 9.542 13.29 9.88 0.554 66.67 200.00 58.75 97.6 7.1 3.0 9.542 12.26 12.39 0.715 66.67 200.00 58.75 114.8 7.1 3.0 9.542 11.36 15.77 1.300 133.33 400.00 48.2 81.5 7.4 3.0 9.542 11.48 14.07 0.928 66.67 200.00 58.75 130.9 7.1 3.0 9.542 11.29 8.34 0.552 66.67 200.00 69.3 114.8 7.1 3.0 9.542 10.29 11.04 0.763 133.33 400.00 58.75 81.5 7.4 3.0 9.542 10.57 10.06 0.674 66.67 200.00 69.3 130.9 7.1 3.0 9.542 9.40 12.85 1.224 133.33 400.00 58.75 97.6 7.4 3.0 9.542 8.65 9.54 0.788 133.33 400.00 69.3 97.6 7.4 3.0 9.542 8.06 6.69 0.601 133.33 400.00 79.85 97.6 7.4 3.0 9.542 7.98 10.88 1.212 133.33 400.00 69.3 114.8 7.4 3.0 9.542 7.43 8.48 0.825 133.33 400.00 79.85 114.8 7.4 3.0 9.542 6.96 9.40 1.172 133.33 400.00 79.85 130.9 7.4 3.0 9.542 9.85 7.13 0.544 66.67 200.00 79.85 130.9 7.1 applications information
ltc6601-2 24 66012f applications information table 7. gain of 2 filter con? gurations gain f o (mhz) f C3db (mhz) q r1 ( ) r2 ( ) c1 (pf) c2 (pf) e in (nv/ hz ) v/v db 2.0 6.021 16.06 18.95 0.868 100.00 200.00 48.2 81.5 8.1 2.0 6.021 14.55 12.69 0.626 100.00 200.00 58.75 81.5 8.1 2.0 6.021 14.68 20.46 1.323 100.00 200.00 48.2 97.6 8.1 2.0 6.021 13.29 15.34 0.840 100.00 200.00 58.75 97.6 8.1 2.0 6.021 12.24 10.96 0.640 100.00 200.00 69.3 97.6 8.1 2.0 6.021 12.26 16.66 1.200 100.00 200.00 58.75 114.8 8.1 2.0 6.021 11.29 12.98 0.835 100.00 200.00 69.3 114.8 8.1 2.0 6.021 10.29 13.97 1.197 200.00 400.00 58.75 81.5 8.5 2.0 6.021 10.51 9.76 0.660 100.00 200.00 79.85 114.8 8.1 2.0 6.021 10.57 13.97 1.102 100.00 200.00 69.3 130.9 8.1 2.0 6.021 9.47 10.52 0.796 200.00 400.00 69.3 81.5 8.5 2.0 6.021 9.85 11.17 0.819 100.00 200.00 79.85 130.9 8.1 2.0 6.021 8.82 7.55 0.616 200.00 400.00 79.85 81.5 8.5 2.0 6.021 8.65 11.91 1.254 200.00 400.00 69.3 97.6 8.5 2.0 6.021 8.06 9.48 0.864 200.00 400.00 79.85 97.6 8.5 2.0 6.021 7.43 10.40 1.341 200.00 400.00 79.85 114.8 8.5 table 8. gain of 1.667 filter con? gurations gain f o (mhz) f C3db mhz q r1 ( )r2 ( ) c1 (pf) c2 (pf) e in nv/ hz v/v db 1.667 4.437 19.67 19.35 0.696 80.00 133.33 48.2 81.5 8.5 1.667 4.437 17.97 22.12 0.934 80.00 133.33 48.2 97.6 8.5 1.667 4.437 16.57 23.16 1.336 80.00 133.33 48.2 114.8 8.5 1.667 4.437 16.28 15.60 0.679 80.00 133.33 58.75 97.6 8.5 1.667 4.437 15.01 17.80 0.875 80.00 133.33 58.75 114.8 8.5 1.667 4.437 14.33 18.58 1.046 80.00 133.33 58.75 126 8.5 1.667 4.437 13.82 13.19 0.676 80.00 133.33 69.3 114.8 8.5 1.667 4.437 12.94 14.77 0.826 80.00 133.33 69.3 130.9 8.5 1.667 4.437 12.06 11.32 0.666 80.00 133.33 79.85 130.9 8.5
ltc6601-2 25 66012f table 9. gain of 1.333 filter con? gurations gain f o (mhz) f C3db mhz q r1 ( )r2 ( ) c1 (pf) c2 (pf) e in nv/ hz v/v db 1.333 2.499 19.67 22.73 0.841 100.00 133.33 48.2 81.5 9.4 1.333 2.499 17.82 15.77 0.633 100.00 133.33 58.75 81.5 9.4 1.333 2.499 17.97 24.34 1.185 100.00 133.33 48.2 97.6 9.4 1.333 2.499 16.28 18.44 0.818 100.00 133.33 58.75 97.6 9.4 1.333 2.499 14.99 13.58 0.646 100.00 133.33 69.3 97.6 9.4 1.333 2.499 15.01 19.82 1.097 100.00 133.33 58.75 114.8 9.4 1.333 2.499 14.06 20.12 1.506 100.00 133.33 58.75 130.9 9.4 1.333 2.499 13.82 15.61 0.814 100.00 133.33 69.3 114.8 9.4 1.333 2.499 12.88 12.03 0.663 100.00 133.33 79.85 114.8 9.4 1.333 2.499 12.94 16.64 1.025 100.00 133.33 69.3 130.9 9.4 1.333 2.499 12.06 13.45 0.801 100.00 133.33 79.85 130.9 9.4 table 10. gain of 1 filter con? gurations gain f o (mhz) f C3db mhz q r1 ( )r2 ( ) c1 (pf) c2 (pf) e in nv/ hz v/v db 1.0 0.0 22.71 25.40 0.804 100.0 100.0 48.2 81.5 10.7 1.0 0.0 20.75 27.23 1.079 100.0 100.0 48.2 97.6 10.7 1.0 0.0 20.57 17.86 0.623 100.0 100.0 58.75 81.5 10.7 1.0 0.0 19.14 27.50 1.543 100.0 100.0 48.2 114.8 10.7 1.0 0.0 18.80 20.62 0.784 100.0 100.0 58.75 97.6 10.7 1.0 0.0 17.31 15.35 0.634 100.0 100.0 69.3 97.6 10.7 1.0 0.0 17.33 22.15 1.011 100.0 100.0 58.75 114.8 10.7 1.0 0.0 16.23 22.58 1.312 100.0 100.0 58.75 130.9 10.7 1.0 0.0 15.96 17.45 0.781 100.0 100.0 69.3 114.8 10.7 1.0 0.0 14.55 19.09 1.079 200.0 200.0 58.75 81.5 11 1.0 0.0 14.87 13.57 0.650 100.0 100.0 79.85 114.8 10.7 1.0 0.0 14.95 18.59 0.954 100.0 100.0 69.3 130.9 10.7 1.0 0.0 13.39 14.90 0.798 200.0 200.0 69.3 81.5 11 1.0 0.0 13.92 15.04 0.769 100.0 100.0 79.85 130.9 10.7 1.0 0.0 12.48 11.38 0.650 200.0 200.0 79.85 81.5 11 1.0 0.0 12.24 16.25 1.115 200.0 200.0 69.3 97.6 11 1.0 0.0 11.40 13.27 0.850 200.0 200.0 79.85 97.6 11 1.0 0.0 11.29 16.47 1.715 200.0 200.0 69.3 114.8 11 1.0 0.0 10.51 14.17 1.167 200.0 200.0 79.85 114.8 11 1.0 0.0 9.47 13.26 1.350 400.0 400.0 69.3 81.5 11.8 1.0 0.0 8.82 10.86 0.935 400.0 400.0 79.85 81.5 11.8 1.0 0.0 8.06 11.57 1.535 400.0 400.0 79.85 97.6 11.8 applications information
ltc6601-2 26 66012f applications information 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r1 57.14 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r1 66.66 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r1 80 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r1 100 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r1 133.33 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 66012 f07 r1 400 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r1 200 15 C + 11 figure 7. pin-strap hookup for a particular r1
ltc6601-2 27 66012f applications information figure 9. pin-strap hookup for a particular c1 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r2 100 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r2 133 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r2 200 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 r2 400 15 C + 11 66012 f08 figure 8. pin-strap hookup for a particular r2 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 c1 48.2pf 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 c1 58.75pf 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 c1 69.3pf 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 c1 79.85pf 15 C + 11 66012 f09
ltc6601-2 28 66012f applications information 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 c2 81.5pf 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 c2 114.8pf 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 c2 97.6pf 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 c2 130.9pf 15 C + 11 66012 f10 figure 10. pin-strap hookup for a particular c2
ltc6601-2 29 66012f applications information example filter con? gurations of basic 2nd order filters figure 11 shows some simpli? ed component hookups of a selection of ? lters taken from tables 7, 9 and 10. for 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 0db f o = 13.92mhz q = 0.769 gain = 0db f o = 22.71mhz q = 0.804 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 6db f o = 9.85mhz q = 0.819 gain = 6db f o = 16.06mhz q = 0.868 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 2.5db f o = 12.06mhz q = 0.801 gain = 2.5db f o = 19.67mhz q = 0.841 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 v out(diff) 66012 f11 v in 15 C + 11 simplicity, v ocm pin bypass and power supply bypass are not shown. figure 11. basic 2nd order filter con? gurations
ltc6601-2 30 66012f figure 12 shows some simpli? ed component hookups of a selection of ? lters taken from tables 4, 5, and 6. for simplicity, v ocm pin bypass and power supply bypass are not shown. applications information 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 12db f o = 6.96mhz q = 0.775 gain = 12db f o = 11.36mhz q = 0.834 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 14db f o = 6.96mhz q = 0.579 gain = 14db f o = 11.36mhz q = 0.614 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 v out(diff) v in 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 9.54db f o = 9.85mhz q = 0.544 gain = 9.54db f o = 16.06mhz q = 0.568 v out(diff) v in 15 C + 11 66012 f12 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 v out(diff) v in 15 C + 11 figure 12. basic 2nd order filter con? gurations
ltc6601-2 31 66012f applications information complex filter configurations a modi? ed 2nd order lowpass filter topology the basic ? lter topology of figure 3 can be modi? ed as shown in figure 13. the figure 13 circuit includes an impedance path between the two summing nodes (the circuit nodes common to resistors r1, r2 and r3). a resistor and/or a capacitor connection between the sum- ming nodes provide even more ? exibility, and enhance the ? lter design options (the f o and q equations shown in figure 13 reduce to equations of figure 3 if c3 is zero and r4 is in? nite). the modi? ed second order ? lter topology provides for setting the q value (with r4) without changing the f o value and increasing the passband gain to greater than one without changing the q value (in the q equation of figure 13 the value of q does not change if the value of the [1 + gain + 2(r2/r4)] denominator factor does not change). using r4 to set the q value allows the option to design the C3db frequency (f 3db ). if the q value varies and the f o value is constant then the f 3db frequency var- ies in a second order lowpass function (refer to the f 3db equation of figure 13). figures 14 to 17 show additional circuits highlighting the use of r4 or c3 in the modi? ed second order cicuit to set the f 3db frequency to 13mhz, 19mhz, 22.7mhz and 24.6mhz respectively. the design procedure for a speci? ed f 3db frequency is as follows: 1 using the chosen c1, c2 and c3 values calculate the f o value. 2. using f o of step 1 and the speci? ed f 3db calculate the q value. 3. calculate the r4 value using the q value of step 3. 4. calculate the required external resistor r ext value for the r4 value in step 3. example, in figure 14 the q value for f 3db = 5mhz is 0.54, the required r4 resistor is 350, the r4a and r4b resistors are the internal 100 and the r ext resistor is 150 [r ext = r4 C (r4a + r4b)]. note: the modi? ed second order ? lter topology requires the use of at least two of the three input resistor pairs (two of the three 400, 200 and 100 pairs).
ltc6601-2 32 66012f applications information figure 13. modi? ed filter topology and equations C + + C v out(diff) 66012 f13 v in(diff) c1 c2 r3 r2 r3 r1 r1 r2 c3a c3b 49.9 r4a r ext r4b c1 c2 r4 = r4a + r4b + r ext c3 = c3a /2 (c3a = c3b) f 3db = f o ? 6089 ? 3568 ? q 4 1788 ? q 2 + 447 () + 1.287 ? 10 5 ?2?q 2 1 () 507.6 ? q q = 0.2236 ? f o ? 2.109 ? 10 5 ? 9.891? 10 12 ?f 3db 4 5.486 ? 10 9 ?f o 4 () + 120 ? 5.526 ? 10 9 ?f 3db 2 + 3.082 ? 10 6 ?f o 2 () 16 ? f o 2 ? 8.29 ? 10 9 ?f 3db 2 + 4.127 ? 10 9 ?f o 2 () 6.638 ? 10 10 ?f 3db 4 () r4 = 1.25 ? 10 4 ?c1?q?r2 559 ? c1? r2 ? c2 + 2?c3 c1 50 ? q ? c1? 125 ? gain + r2 + 125 () c2 ? r2 () v out(diff) v in(diff) = C gain r2 ? r3 ? c1? c2 + 2?c3 () s 2 + r1? r2? 2?r3 + r4 () + r3 ? r4 () + r2 ? r3 ? r4 r1?r2?r3?r4? c2 + 2?c3 () ?s + 1 r2 ? r3 ? c1? c2 + 2?c3 () gain = C v out(diff) v in(diff) = C r2 r1 f o = 1 2? ?r2?r3?c1?c2 + 2?c3 () q = r3 r2 ? c2 c1 + 2? c3 c1 1 + 1 + |gain| + 2? r2 r4 ? r3 r2 C c2 c1
ltc6601-2 33 66012f figure 14. modi? ed filter con? guration using a resistor between summing nodes (f C3db = 13mhz) applications information 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 1 f o = 11.28mhz q = 0.835 f C1db = 10mhz f C3db = 13mhz v out(diff) v in(diff) z in(diff) = 400 v in(diff) z in(diff) = 200 15 C + 11 200 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 2 f o = 11.28mhz q = 0.835 f C1db = 10mhz f C3db = 13mhz v out(diff) 15 C + 11 66012 f14a frequency (hz) gain (db) 66012 f14b 5 0 C10 C5 C15 C20 C25 C30 C35 C40 100k 100m 10m 1m frequency (hz) phase (deg) group delay (ns) 66012 f14c 30 0 C30 C60 C90 C120 50 40 30 20 10 0 0 100k 4m 12m 16m 8m phase group delay gain magnitude vs frequency (gain = 1) passband phase and group delay
ltc6601-2 34 66012f applications information figure 15. modi? ed filter con? guration using a resistor between summing nodes (f C3db = 19mhz) frequency (hz) gain (db) 66012 f15b 5 0 C5 C10 C15 C20 C25 C30 C35 C40 100k 100m 10m 1m frequency (hz) phase (deg) group delay (ns) 66012 f15c 30 0 C30 C60 C90 C120 50 40 30 20 10 0 0 100k 4m 16m 20m 12m 8m phase group delay gain magnitude vs frequency (gain = 1) passband phase and group delay 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 1 f o = 16mhz q = 0.868 f C1db = 15.4mhz f C3db = 19mhz v out(diff) v in(diff) z in(diff) = 400 v in(diff) z in(diff) = 200 15 C + 11 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 2 f o = 16mhz q = 0.868 f C1db = 15.4mhz f C3db = 19mhz v out(diff) 15 C + 11 66012 f15a 200
ltc6601-2 35 66012f applications information figure 16. modi? ed filter con? guration using a resistor between summing nodes (f C3db = 22.7mhz) v in(diff) z in(diff) = 200 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 1.33 f o = 19.7mhz q = 0.84 f C1db = 19mhz f C3db = 22.7mhz v out(diff) 15 C + 11 66012 f16a v in(diff) z in(diff) = 266 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 gain = 1 f o = 19.7mhz q = 0.84 f C1db = 19mhz f C3db = 22.7mhz v out(diff) 15 C + 11 33.2 33.2 frequency (hz) gain (db) 66012 f16b 5 0 C10 C5 C15 C20 C25 C30 C35 C40 100k 100m 10m 1m frequency (hz) phase (deg) group delay (ns) 66012 f16c 30 0 C30 C60 C90 C120 50 40 30 20 10 0 0 100k 4.6m 18.4m 23m 13.8m 9.2m phase group delay gain magnitude vs frequency (gain = 1) passband phase and group delay
ltc6601-2 36 66012f applications information figure 17. modi? ed filter con? guration using a capacitor between summing nodes (f C3db = 24.6mhz) gain = 1 f o = 20.7mhz q = 0.88 f C1db = 20.5mhz f C3db = 24.6mhz v in(diff) z in(diff) = 200 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 v out(diff) 49.9 15 C + 11 66012 f17a frequency (hz) gain (db) 66012 f17c 5 0 C10 C5 C15 C20 C25 C30 C35 100k 100m 10m 1m frequency (hz) phase (deg) group delay (ns) 66012 f17d 30 0 C30 C60 C90 C120 50 40 30 20 10 0 0 100k 5.2m 20.8m 26m 15.6m 10.4m phase group delay gain magnitude vs frequency (gain = 1) passband phase and group delay frequency (hz) gain (db) 66012 f17b 1.0 0.5 0.0 C1.0 C0.5 C1.5 C2.0 C2.5 C3.0 100k 40m 10m 1m passband gain vs frequency
ltc6601-2 37 66012f applications information dc1251a demonstration board the dc1251a demonstration circuit contains an ltc6601-2 (dc1251a-b). on a dc1251a the ltc6601 programming pins can be connected through 0603 resistor jumpers. in addition, optional surface mount capacitors and inductors at the ltc6601 input and/or output can be installed for additional ? ltering (a lowpass ? lter up to a 5th order can be implemented with a dc1251a demonstration circuit). the dc1251a has sma connectors for the differential input and output of the ltc6601. an on board 106mhz lowpass rc ? lters the ltc6601 output. dc1251a top silk screen
ltc6601-2 38 66012f applications information ltc6601-x demonstration circuit dc1251a 66012 dc r c3 in2+ in1+ bias in1C in2C 1 2 3 4 5 15 14 13 12 11 out v+ vC v ocm out in3+ c5 c6 c7 c8 20 19 18 ltc6601-2 17 16 678910 inC c1 c2 c3 c4 r c2 r q1 r5 20 1% (opt) r4 20 1% (opt) r f1 r f2 r f3 r f4 r f5 r f6 r f7 r f8 r f9 r f10 r f11 r f12 r1 49.9, 1% r2 49.9, 1% r3 49.9, 1% c11 1000pf c10 0.01f v+ c8 10pf c9 10pf c7 10pf c3 (opt) c4 (opt) c12 0.01f j3 v outC j4 v out+ e3 ext v ocm e4 gnd (24aqg-via) (24awg-via) r g2 r g1 r z1 c5 (opt) r in1 r z2 r g4 r g5 r g6 r g3 c6 (opt) c2 (opt) c1 (opt) r in2 j1 v in + j2 v in C 1 3 5 2 4 6 hp lp shdn v + jp1 c15 0.1f c14 1f 10v c13 10f 10v e1 v+ in 2.7v to 5.5v e2 gnd (24awg-via) (24awg-via) v + dc1251a-a ltc6601cuf-1#tr dc1251a-b ltc6601cuf-2#tr assy u1 board assembly
ltc6601-2 39 66012f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uf package 20-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1710) 4.00 p 0.10 (4 sides) note: 1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-1)to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.38 p 0.10 20 19 1 2 bottom viewexposed pad 2.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf20) qfn 10-04 recommended solder pad pitch and dimensions 0.70 p 0.05 0.25 p 0.05 0.50 bsc 2.45 p 0.05 (4 sides) 3.10 p 0.05 4.50 p 0.05 package outline pin 1 notch r = 0.30 typ
ltc6601-2 40 66012f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2009 lt 0309 ? printed in usa part number description comments lt ? 1568 very low noise, high frequency, active rc, filter building block up to 10mhz filters, snr = 92db, thd = C84dbc at 2mhz lt1993-2/lt1993-4/ lt1993-10 800mhz/900mhz/700mhz low distortion, low noise differential ampli? er/adc driver a v = 2v/v / a v = 4v/v / a v = 10v/v, nf = 12.3db/14.5db/12.7db, oip3 = 38dbm/40dbm/40dbm at 70mhz lt1994 low noise, low distortion fully differential input/output ampli? er/driver low distortion, 2v p-p , 1mhz: C94dbc, 13ma, low noise: 3nv/ hz lt6402-6/lt6402-12/ lt6402-20 300mhz low distortion, low noise differential ampli? er/ adc driver a v = 6db/a v = 12db/a v = 20db, nf = 18.6db/15db/12.4db, oip3 = 49dbm/43dbm/51dbm at 20mhz ltc6404-1 fully differential ampli? er, gbw = 500mhz very low distortion, (2v p-p , 10mhz): C91dbc ltc6404-2 fully differential ampli? er, gbw = 900mhz very low distortion, (2v p-p , 10mhz): C96dbc ltc6404-4 fully differential ampli? er, gbw = 1700mhz very low distortion, (2v p-p , 10mhz): C101dbc lt6600-2.5/lt6600-5/ lt6600-10/lt6600-20 very low noise, fully differential ampli? er and filter 2.5mhz/5mhz/10mhz/20mhz integrated filter, 3v supply, so-8 package ltc6601-1 low noise, pin-con? gurable filter 5mhz to 27mhz bandwidth, second order differential filter ltc6602 dual, matched bandpass filter programmable gain and bandwidth for rfid applications (40khz to 1mhz) ltc6603 dual, matched lowpass filter programmable gain and bandwidth (25khz to 2.5mhz) lt6604-x dual, matched lowpass filter 2.5mhz, 5mhz, 10mhz and 15mhz ltc6605-x dual, matched lowpass filter 7mhz, 10mhz and 14mhz typical application 5th order, 20mhz, lowpass filter gain magnitude vs frequency related parts passband gain vs frequency frequency (hz) gain (db) 66012 ta02c 1.0 0.5 C0.5 0 C1.0 C1.5 C2.0 C2.5 C3.0 100k 10m 1m frequency (hz) gain (db) 66012 ta02b 10 0 C20 C10 C30 C40 C50 C60 C70 100k 100m 10m 1m v in(diff) z in(diff) = 266 33.2 20 19 18 17 16 1 2 4 5 6 7 8 9 10 ltc6601-2 v out(diff) 15 C + 11 33.2 66012 ta02a 270pf 82pf 220nh* 220nh* *coilcraft 0603cs 82pf 82pf

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